Engineering
5. 10 In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2P1L1 Size, 2 KiBL1 Miss Rate, 8. 0%L1 Hit Time, 0. 66nsP2L1 Size, 4 KiBL1 Miss Rate, 6. 0%L1 Hit Time, 0. 90nsFor the next three problems, we will consider the addition of an L2 cache to P1 (to presumably make up for its limited L1 cache capacity). Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate,L2 Size, 1 MiBL2 Miss Rate, 95%L2 Hit Time, 5. 62nsQUESTION TO ANSWER (MAKE SURE YOU ACTUALLY ANSWER THE QUESTION ASKED): What would the L2 miss rate need to be in order for P1 with an L2 cache to be faster than P2 without an L2 cache?